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C4-0 is an utterly pointless computer from scratch.

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Architecture

+-----------------------------------------------------------------------------+
| Local Integrated Management Bits  (LIMB / EC)                               |
|                                                                             |
|       +-------------------------+         +-------------------------+       |
|       | Master Interface        |         | Slave Interface         |       |
|       |=========================|         |=========================|       |
|       | Power sequencing        |         | SD card interface       |       |
|       | FPGA initialization     | ------> | UARTs, I2C              |       |
|       | Bootloader loading      |         | Sensor readback         |       |
|       | Sensor monitoring       |         |                         |       |
|       +-------------------------+         +-------------------------+       |
|                           |                  ↑                  Atmel SAM4S |
+---------------------------|------------------|------------------------------+
                            |                  |
                            ↓                  |
+-------------+         +--------------------------+            +-------- - - -
| Memory      |         | Northbridge              |            | PCI bus
|             | <-----> |                          | <--------> |
| DDR3-SODIMM |         | Xilinx XC6SLX45          |            | 4 slots
+-------------+         +--------------------------+            +-------- - - -
                            ↑                   ↑
                            ↓                   ↓
                +-----------------+         +-----------------+
                | CPU 0           |         | CPU 1           |
                |                 |         |                 |
                | Xilinx XC6SLX45 |         | Xilinx XC6SLX45 |
                +-----------------+         +-----------------+
                         ↑                           ↑
                         ↓                           ↓
                    +---------+                 +---------+
                    |  Cache  |                 |  Cache  |     ???
                    +---------+                 +---------+

Hardware

Motherboard 3D render

Hardware design is currently ongoing. Click the preview to see a full-size render (56k warning!)

LIMB

The LIMB (Local Integrated Management Bits) is an ARM microcontroller performing two main tasks, mostly depending on the operational mode of the system:

Master process

The LIMB master process gets the system running. On boot, it performs the following sequence of tasks:

  1. Storage initialization. SD card presence is checked, the partition table is read, all required files are located, and any checksums are validated.
  2. Power sequencing. Power supplies are activated, and monitored until they reach a stable state.
  3. FPGA loading. FPGA bitstreams are read into the FPGAs from the SD card, and the control interfaces are tested to validate that they are functioning.
  4. Clock setup. The clock synthesizer is programmed to the correct bus, RAM and CPU frequencies.
  5. Memory loading. The bootloader binary is read from the SD card into SDRAM and read back to validate.
  6. Run. CPU0 is released from its reset vector and begins running.

In addition, the following services are provided during runtime:

  1. Interrupt generation. A few interrupts, including a system timer interrupt, are provided to the CPUs.
  2. Sensor monitoring. Sensors, including power supply voltage and current, temperatures, and fan speeds, are monitored constantly. The CPUs can read these values through the slave interface as memory-mapped registers, but the master process will also monitor them and shut down the system if necessary for safety.

Slave process

The LIMB slave process provides services to both the master process and the northbridge (and thus to the rest of the system). The following services are provided:

  1. UARTs. A pair of UARTs, one virtual (USB-CDC) and one RS-232, are exposed to the system. The virtual UART is used by the master for debug messages, and can also sink debug messages from the CPUs. The RS-232 UART is fully exposed for the system for use by the operating system.
  2. I2C, SMBUS. What it sounds like. A number of peripherals, including the power supply, debug status LEDs, SDRAM SPD EEPROM, RTC, PCI SMBUS segment, and so on are provided through this.
  3. Storage interface. The SD card is provided to the system as a block device for general-purpose use by the operating system. Additionally, a simple file-level interface is provided to simplify bootloaders and allow them to take advantage of the partition table and file system drivers already in the LIMB.

Northbridge

The northbridge is a Xilinx Spartan-6 FPGA providing DDR3 controller, PCI bus master, interfaces to the custom LIMB and CPU buses, and a memory management unit.

CPU

The CPUs are Xilinx Spartan-6 FPGAs implementing a custom CPU architecture using a mostly MIPS-compatible instruction set. These will be multicore as FPGA fabric space allows, and may or may not have external cache RAM. A design goal is for them to be as simple as possible in terms of logic element consumption, allowing a system as parallel as possible to compensate for the low clock rate of the FPGA.

PCBs

Firmware

Written by Chris Pavlina. CC0 1.0 Universal

Last modified: Thu Sep  1 10:33:02 EDT 2016